1. Field of the Invention
The present invention relates generally to the field of programmable logic devices such as electrically programmable read only memories and more specifically, to a logic element which forms the basic logic cell of a programmable element array wherein the circuit of each such cell employs threshold modifiable transistors as permanent memory storage devices which control the logic operation of the circuit and which may be modified by changing the programming state or threshold of the memory transistors used in the circuit.
2. Prior Art
Conventional electrically programmable read only memories (EPROM) employ a transistor with an alterable switching threshold as a memory device. Such transistors are programmed on or off by threshold change and then scanned by selection electronics to read their contents. This prior art scanning approach requires relatively high bias power consumption in the read electronics and does not apply a holding voltage to the programmed transistor. Consequently, such prior art suffers two distinct disadvantages, namely, high bias power consumption for read out and shorter than desirable program retention time for long term logic applications. As a result, conventional electronically programmed read only memories generally require more complex electronics and therefore, more costly electronics. In addition, they require higher bias power consumption in the read electronics than is generally desirable. There is therefore a current need for an EPROM circuit design which substantially reduces or entirely eliminates high bias power consumption on read electronics as well as providing a means for extending the program retention time of the programmed transistor memory devices.
In a prior art search conducted by the applicant, thirteen patents of varying relevance were found but none reduces the bias power consumption and none provides a sustained programming voltage design to overcome the noted deficiencies of the prior art. These patents consist of the following:
U.S. Pat. No. 4,090,258 Cricchi PA1 U.S. Pat. No. 4,103,185 Denes PA1 U.S. Pat. No. 4,122,544 McElroy PA1 U.S. Pat. No. 4,149,270 Cricchi et al PA1 U.S. Pat. No. 4,170,741 Williams PA1 U.S. Pat. No. 4,192,016 Taylor PA1 U.S. Pat. No. 4,193,128 Brewer PA1 U.S. Pat. No. 4,236,231 Taylor PA1 U.S. Pat. No. 4,399,523 Gerber et al PA1 U.S. Pat. No. 4,446,536 Rodgers PA1 U.S. Pat. No. 4,554,643 Kuo PA1 U.S. Pat. No. 4,575,823 Fitzpatrick PA1 U.S. Pat. No. 4,599,705 Holmberg et al
Of the aforementioned thirteen patents, the following are deemed to be the most relevant to the present invention.
U.S. Pat. No. 4,192,016 to Taylor is directed to a CMOS-bipolar EAROM. The memory circuit described in this reference consists of switchable amorphous storage elements, each with an isolation transistor. These isolation transistors are NPN bipolar transistors configured as emitter follows. The circuit uses a clocked operation to reduce the power consumption, and the use of the bipolar NPN transistors reduce the amount of overall area required per cell on the integrated circuit. Thus, this reference describes a buffered switching threshold memory device like the subject disclosure. However, it does not provide the sustaining programming voltage applied to the programmed transistors, as is the case in the subject disclosure, nor is the circuit configuration the same as the subject disclosure.
U.S. Pat. No. 4,599,705 to Holmberg et al is directed to a programmable cell for use in programmable electronic arrays. The reference describes a memory cell for use in programmable logic arrays like the subject disclosure. A switching threshold memory device is used with an isolating device such as a bipolar or MOS type device. Although each memory cell has an isolation device such is not used to eliminate the bias power consumed in the electronics, as is the case of the subject disclosure. Nor does the referenced circuit have a sustaining programming voltage applied to the programmed transistors as does the circuit of the subject disclosure.
U.S. Pat. No. 4,193,128 to Brewer is directed to a high density memory with non-volatile storage array. This reference describes a memory device which incorporates both volatile and non-volatile memory cells. The non-volatile memory cells are made up of a pair of MNOS transistors which store information in accordance with the state of their threshold voltage. These memory cells do not include any buffering, as is the case of the subject disclosure, nor do they provide a sustaining programming voltage to the programmed transistors.
U.S. Pat. No. 4,554,643 to Kuo is directed to an electrically erasable programmable MNOS read only memory. An EPROM memory cell is described where the cell is composed of two transistor elements. The storage element is an MNOS transistor which is the alterable switching threshold device, and coupled in series is an MOS transistor to provide isolation and the needed drive during the read cycle. The buffered read cycle does not reduce the bias power consumption, as is the case of the subject disclosure, nor is programming voltage sustained as is the case of the subject disclosure.
U.S. Pat. No. 4,575,823 to Fitzpatrick is directed to an electrically alterable non-volatile memory. Two variable threshold transistors make up the memory cell of the device described in this reference. While buffer circuits are provided for the device, they are not included in each memory cell, as is the case of the subject disclosure. The sustained programming voltage is also not present in this reference.